Computer architecture questions need all of them solved CSC
Solution
Basic Needful Information to Solve Problem:
^ means complement .(Ex : Treat A^ means Complement of A)
Truth Table for Exclusive Or Gate :
A
B
Result
0
0
1
0
1
0
1
0
0
1
1
1
Truth Table D-Flip Flop
Q(t)
Q(t+1)
0
0
1
1
Truth Table D-Flip Flop
JK latch truth table
J
K
Qnext
Comment
0
0
Q
No change
0
1
0
Reset
1
0
1
Set
1
1
Q
Toggle
Explanation :
Question1 :
We are assuming clock pulse are applying at a time to all flipflops in ckt,now D flip lop produce same input as ouput and JK flip flop produce if input is 0 0 no change in output, if input is 0 1 then output is 0, if input is 1 0 out put is 1, if input is 1 1 then output is toggled.
Ex: if A=0,B=0,X=0 then D flipflop output (Anext state) is value of B and JK flipflop output (B next state) is produced with two inputs values exclusive –or function(Not B,A=>1,0) à 0 ,X(0).
D flipflop output 0,Jk flipflop output 0.
The process is continued for all input variable s below table obtained
A
B
X
Anext
Bnext
0
0
0
0
0
0
0
1
0
0
0
1
0
1
1
0
1
1
1
0
1
0
0
0
1
1
0
1
0
1
1
1
0
1
1
1
1
0
1
0
Finally Equations Anext(A,B,X) =F(B) & Bnext (A,B,X)= ^AB^X+AB^X^+AB^X+ABX^
Question2 :
We are assuming clock pulse are applying at a time to all flipflops in ckt,now D flip lop produce same input as output .
Ex: if A=0,B=0,X=0 then D flipflop output (Anext state) is value of B and JK flipflop output (B next state) is produced with two inputs values exclusive –or function(Not B,A=>1,0) à 0 ,X(0).
D flipflop output 0,Jk flipflop output 0.
The process is continued for all input variable s below table obtained
A
B
X
Anext
Bnext
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
0
1
0
0
0
1
1
0
1
1
1
1
1
0
1
1
1
1
0
0
1
Finally Equations Anext(A,B,X) =A^B^X+A^BX^+AB^X+ABX^ & Bnext (A,B,X)= F(A)
| A | B | Result |
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |




