Following the behavioral description example provided in Sec

Following the behavioral description example provided in Section 6.3, write up a VHDL code for the above FSM with one hot state assignment. Do not forget to include the implementation of the 7 segment output decoding logic in the same code.

6.3 FSM Description Using VHDL Behavioral constructs are often utilized in VHDL to describe a Finite State Machine. For the simple FSM described in the below table, a coding example follows with some explanation. Next State Present State METU Northern Cyprus Campus EEE 248/CNG 232 (Spring 2016) LIBRARY ieee; USE ieee.std.logic.1164.all; ENTITY simple IS PORT (Clock, Resetn, IN STD LOGIC: OUI STD LOGIC) END simple ARCHITECTURE Behavior OF simple IS SIGNAL y present, y next STD LOGIC_VECTOR (1 DOWNTO 0) CONSTANT A STD LOGIC VECTOR ( 1 DOWNTO 0) := \"00\'\"; CONSTANT B STD LOGIC VECTOR ( 1 DOWNTO 0) := \"01\'\"; CONSTANT C : STD LOGIC VECTOR (1 DONTO 0) := w11\". BEGIN PROCESS (w, Y present) CASE y present IS WHEN A => IF w=, 0, THEN ,next

Solution

There is a special Coding style for State Machines in VHDL as well as in Verilog.

Let us consider below given state machine which is a “1011” overlapping sequence detector. Output becomes ‘1’ when sequence is detected in state S4 else it remains ‘0’ for other states

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Sequence detector for detecting the sequence \"1011\".
--Overlapping type.
entity seq_det is
port(   clk   : in std_logic;      --clock signal
        reset : in std_logic;      --reset signal
        S_in : in std_logic;      --serial bit Input sequence    
        S_out : out std_logic);    -- Output         
end seq_det;
architecture Behavioral of seq_det is
--Defines the type for states in the state machine
type state_type is (S0,S1,S2,S3,S4);
--Declare the signal with the corresponding state type.
signal Current_State, Next_State : state_type;
begin
-- Synchronous Process
process(clk)
begin
    if( reset = \'1\' ) then                 --Synchronous Reset
        Current_State <= \'S0\';
    elsif (clk\'event and clk = \'1\') then   --Rising edge of Clock
        Current_State <= Next_State
    end if;
end process;
-- Combinational Process
Process(Current_State, S_in)
    begin
        case Current_State is
            when S0 =>                      
                S_out <= \'0\';
                if ( s_in = \'0\' ) then
                    Next_State <= S0;
                else    
                    Next_State <= S1;
                end if;
            when S1 =>
                S_out <= \'1\';   
                if ( S_in = \'0\' ) then
                    Next_State <= S3;
                else    
                    Next_State <= S2;
                end if;
            when S2 =>
                S_out <= \'0\';   
                if ( S_in = \'0\' ) then
                    Next_State <= S0;
                else    
                    Next_State <= S3;
                end if;
            when S3 =>
                S_out <= \'1\';   
                if (S_in = \'0\' ) then
                    Next_State <= S2;
                else    
                    Next_State <= S4;
                end if;
            when S4 =>
                S_out <= \'1\';   
                if ( S_in = \'0\' ) then
                    Next_State <= S2;
                else    
                    Next_State <= S1;
                end if;
            when others =>
                NULL;
        end case;
    end if;
end process;