Create a source file for an 8bit D register with both a sync

Create a source file for an 8-bit D register with both a synchronous reset (named SRST) and an asynchronous reset (named ARST). Simulate the register, showing all pertinent operating states. Submit your source code and simulation outputs.

Solution

module reg8 (reset, CLK, D, Q);

input reset;

input CLK;

input [7:0] D;

output [7:0] Q;

reg [7:0] Q;

always @(posedge CLK)

if (reset) Q = 0;

else Q = D;