Write the VHDL code for the 8output demultiplexer shown belo

Write the VHDL code for the 8-output demultiplexer shown below using the case statement: LIBRARY ieee; USE ieee.std_togic_1164.ALL; ENTITY demux IS PORT(: STD. LOGIC.VECTOR (_DOWNTO 0);: STD.LOGIC;: STD_L0GIC_VECTOR (_ DOWNTO 0)); END demux; ARCHITECTURE arc OF IS BEGIN PROCESS() BEGIN CASE IS WHEN \" \"

Solution

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity demux is
port(
din : in STD_LOGIC;
s : in STD_LOGIC_VECTOR(1 downto 0);
dout : out STD_LOGIC_VECTOR(7 downto 0)
);
end demux;

architecture arc of demux is
Begin
PROCESS(din,sel)
Begin
case sel is
when \"000\" => dout <= (din & \"0000000\");
when \"001\" => dout <= (\'0\' & din & \"000000\");
when \"010\" => dout <= (\"00\" & din & \'00000\');
when \"011\" => dout <= (\"000\" & din & \'0000\');
when \"100\" => dout <= (\"0000\" & din & \'000\');
when \"101\" => dout <= (\"00000\" & din & \'00\');
when \"110\" => dout <= (\"000000\" & din & \'0\');
when others => dout <= (\"0000000\" & din);
end case;
end process;
end arc;