E xercises box in Section 14 that produces the oscillating v

E xercises box in Section 1.4) that produces the oscillating voltage shown in Figure 4.5b. Note the resemblance of that voltage to the conductor\'s baton. Every machine cycle, the voltage rises to 2.9 volts and then drops back to 0 volts. If the RUN latch is in the l state (ie, Q = 1), the output of the clock circuit is the same as the output of the clock generator. If the RUN latch is in the 0 state (i.e..-0), the output of the clock circuit is 0. Thus, stopping the instruction cycle requires only clearing the RUN lat Thus, stopping the instruction cvele eoui eteasinn sa DtNI h Every computer has some mechanism for doing that. In some older machines, it is done by executing a HALT instruction. In the LC-3, as in many other machines it is done under control of the operating system, as we will sce in Chapter 9 Question: If a HALT instruction can clear the RUN latch, thereby stopping the instruction cycle, what instruction is needed to set the RUN latch, thereby reinitiating the instruction cycle? Exercises 4.1 Name the five components of the von Neumann model. For each component, state its purpose. 4.2 Briefly describe the interface between the memory and the processing unit. That is, describe the method by which the memory and the processing unit communicate. What is misleading about the name program counter? Why is the name instruction pointer more insightful? What is the word length of a computer? How does the word length of a computer affect what the computer is able to compute? That is, is it a valid argument, in light of what you learned in Chapter 1, to say that a computer with a larger word size can process more information and therefore is capable of computing more than a computer with a smaller word size? The following table represents a small memory. Refer to this table for the following questions. 4.3 2 4.4 4.5 Data Address 0000 0001 1110 0100 0011 0001 1111 0000 00100101 0010 0110 1111 0000 0001 0011 00000000 0000 0000 0100 0000 0000 0110 0101 0101 0000 0000 0000 0110 0111 0000 0110 1101 100

Solution

4.8 (a). Minimum number of bits required to represent OPCODE is 8 bits.

(b) Minimum number of bits required to represent Destination Register is 7 bits.

(c) total bits = 32 bits

opcode bits = 8bits

DR bits = 7 bits

SR1 bits = 7 bits

SR2 bits = 7 bits

therefor no of UNUSED bits are : 32-8-7-7-7 = 3 bits

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