Answer the questions that follow the VHDL code given below L

Answer the questions that follow the VHDL code given below. LIBRARY ieee; USE ieec.std logic 1164.ALL; ENTITY ex 1 IS PORT(n_cp, n rd: IN stdlogic; q: BUFFER integer RANGE 0 TO 15); END ex 1; ARCHITECTURE arc OF ex 1 IS BEGIN PROCESS (n cp, n rd) BEGIN IF (n_rd=\'0\') THEN q

Solution

A) Input variables n_cp and n_rd are representing number of clock pulses.

B) There are 4 bits in the output q.

C) It is an up counter.

D) It is MOD10 counter.

E) The counter counts negative edge of the clock .

F) \"if(n_cp\'EVENT) then if(n_cp=\'0\')then\" can be used instead of given vhdl statement .