Homework SourseWhat is the difference between timer and counter functions I
Solution
Timer Functions
• T0TCR, T1TCR, T2TCR, T3TCR
• Control the timer/counter functions.
• The Timer Counter can be disabled or reset through the TCR.
• Bit [31:2] : reserved
– user software should not write ones to reserved bits.
• Bit [1] : Counter reset
– ‘1’ : reset Timer Counter (TC) and Prescale Counter (PC)
• Bit [0] : Counter enable
– ‘1’ : the Timer Counter and Prescale Counter are enabled for counting.
• Reset : TCR = 0x02
• Enabled : TCR = 0x01
Counter Functions
T0CTCR, T1CTCR, T2CTCR, T3CTCR
• Bit [31:4] : reserved
– user software should not write ones to reserved bits.
• Bit [3:2]
– It is used when bit [1:0] are not ‘00’.
• Counter mode
– ‘00’ : CAPn.0 for TIMERn
• See CCR.
• Set CCR [2:0] => ‘000’
– ‘01’ : CAPn.1 for TIMERn
• See CCR.
• Set CCR [5:3] => ‘000’
• Bit [1:0] : Counter/Timer mode
– ‘00’ : Timer mode
• TC is incremented when the Prescale Counter (PC) matches the Prescale
Register (PR).
• The Prescale Counter is incremented on every rising PCLK edge.
– ‘01’,’10’, ‘11’ : Counter mode
• TC is incremented
– ‘01’ : on rising edges on the CAP input selected by bits 3:2.
– ‘10’ : on falling edges on the CAP input selected by bits 3:2.
– ‘11’ : on both edges on the CAP input selected by bits 3:2.
IR - Interrup Register
• T0IR, T1IR, T2IR, T3IR
• The IR can be read to identify which of eight possible interrupt sources
are pending.
• Writing ‘1’ : clear interrupt flag.
• Bit [31:6] : reserved
• Bit [5] : CR1 Interrupt flag
– capture channel 1 event
• Bit [4] : CR0 Interrupt flag
– capture channel 0 event
11
• Bit [3] : MR3 Interrupt flag
– match channel 3
• Bit [2] : MR2 Interrupt flag
– match channel 2
• Bit [1] : MR1 Interrupt flag
– match channel 1
• Bit [0] : MR0 Interrupt flag
– match channel 0
