ADVANTAGES OF CNTFET OVER DOUBLE GATE MOSFET IN NANOMETER RE

ADVANTAGES OF CNTFET OVER DOUBLE GATE MOSFET IN NANOMETER REGIME. can any one write a research paper on this topic of 12 pages with 0% plagiarism

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Paper on Carbon Nanotube Field Effect Transistor (CNTFET) over MOSFET

Abstract– Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) have started offering their performance limitations at deep sub-micron technologies. This opens new avenues for exploring the novel materials and devices for future electronics design applications. It is seen that the Carbon Nanotube Field Effect Transistor (CNTFET) has superior performance over MOSFETs. The CNFETs have a very small Power Delay product (PDP) that adds up to a 50% of speed improvement in comparison to a multi-valued inverter, which makes it area efficient. In nanometer regime, the quantum capacitance plays a major role in deciding the gate capacitance of CNTFETs; accordingly it needs an extra attention and shall be considered carefully while scaling down the device. In this paper, a comparative study has been performed and it is seen that in a nanoscale regime, the CNTFET devices are advantageous over MOSFETs due to their reduced quantum capacitance, as the value of quantum capacitance is an increasing issue in MOSFETs that leads to an increased propagation delay and hence leads to performance degradation.

Keywords–Carbon Nanotube FET, MOSFET, Quantum capacitance, Power delay product (PDP), Neural Networks.

For the past three decades the scaling of MOSFET has been the driving force towards the technological advancement. However, for Very Large Scale Integration Systems which depends on Silicon MOS Technology, Industry Technology Road Map (ITRS) has predicted that in nano regimes the expected high density integration will encounter substantial difficulties due to fundamental physics, material and

manufacturing obstacles. The effects of continuous scaling include short channel effects, high leakage current, excessive process variation and reliability issues. These limits can be overcome to some extent by modifying the channel material in the traditional bulk MOSFET structure with the single Carbon Nanotube or an Array of Carbon nano tubes.

Currently most of the models which are developed for CNT Transistors and interconnect possess numerical approaches [1] to obtain the device characteristic. Such numerical approaches degrade the computation efficiency and are not suitable for circuit simulations. So, neural network seems to be very promising approach to model the CNT transistors. Neural network has the capability of approximating any non linear function with the ability of being trained by experimental or device simulation data. If the network is trained once it can be used many times for a given modeling problem. Their equations are simple, continuous and derivable which suits well with the analog simulators especially from the convergence perspective [2].

Carbon Nanotubes are new form of carbon with unique electrical and mechanical properties [3]-[4]. They are cylindrical sheets of one or more concentric layers of carbon atoms. Their band structure depends on the position of carbon atom forming the tube. Nanotubes can be metallic or semiconducting depending on the folding angle and diameter. Simple theory [5] also shows that band gap of semiconducting CNTs decrease with increasing diameter. Metallic CNT for example were utilized as Coulombs Island in single electron transistor [6]-[7] and very recently Tans and his co-workers built a molecular Field Effect Transistor with the Semiconducting Nanotube [8]-[9]. The advantages of CNT technology are quite significant. It improves mechanical and conductive behavior, optimizes processing fabrication and reduces shipping cost, enables eco-friendly anti falling pins and other new applications, Enables clean bulk micro machining and assembly of electronic components and lastly it improves the true total cost of formulation, processing and manufacturing.

Fig.1: CNTFET structure, similar to that of MOSFET

CNTs are hexagonal networks of carbon atoms 1nm in diameter and 1-100 m in length and can be taken as a layer of graphite rolled up into a cylinder. CNTFET utilizes semiconducting single wall to assemble electronic devices [10].

In this device, depicted in Fig.2a), the ungated regions (source and drain regions) are heavily doped and it operates on the principle of barrier-height modulation by application of the gate potential

(Fig. 2b).

In this case, the on-state current is limited by the amount of charge introduced in the channel by the gate and, for source-drain distances shorter than 150nm, the transport is assumed to be free of significant scattering and thus essentially ballistic at both high and low voltages. Hence, the description of current flow through the CNT lies on (i) the features of ballistic transport and (ii) the specific electron confinement along the tube circumference [12]:

Fig.2a): Schematic design features with high K-dielectric.b) The Band diagram with,at Vg=0V<the barrier height at the source channel junction is Eg/2.[11]

Fig. 3. The SWNT energy versus wave-number (E-k) diagram. a) the source and drain Fermi level have been shown by ìS and ìD. b) Dp with p=1,2,3,… are the minima of the energy subbands.[11]

k

As V_G, the gate bias, modulates the top of the energy

barrier; it lowers the channel potential by an amount V_CNT and causes accumulation of charge in the channel, Q_CNT.This charge Q_CNT induces a voltage drop V_G-V_CNT across the high K insulator which causes the energy bands to be lowered by V_CNT. This self consistent loop in C-CNTFET operation cannot be handled in a circuit-compatible model, necessarily based on a linear analytical development. Hence, the compact model proposed by A. Raychowdhury [14] lies on the calculation of the channel potential V_CNT through fitting parameters of the channel charge, Q_CNT.

The modulation of the channel potential, V_CNT throughthe gate bias, V_G, results from the presence of the charge in the channel, Q_CNT:

V_CNT = V_GS –(Q_CNT/C) ………………….(1)

Where,

1/C = 1/C_ox + 1/C_Q

   C_Ox being the gate capacitance and CQ the quantum capacitance.

The total charge on the nanotube, QCNT depends on the number of carrier in the channel, nCNT which results from the specific electron confinement along the tube circumference mentioned above [15][16]. As a consequence, its expression is the sum of the energy subband contributions:

with

The drain current equation derives from the Landauer

[13] formula which describes the ballistic transport with perfect contacts. Its expression represents the sum of the energy subband contributions of two terms. The first term represents the occupation of the +k states from the source up to µ_S and the other represents the occupation of the –k states from the drain up to µ_D; the difference between µ_S and µ_D results from the bias VDS applied between source

and drain (Fig. 2a)):

                                                                           … (3)

Where, e is the electron charge, kB is the Boltzmann

constant, h is the Planck’s constant and T the temperature. Since it is not possible to obtain an analytical closed form expression for the integral given in (2), A. Raychowdhury has proposed the following fitting expression:

                                                               

                                                                          … (4)

   

With = _{0 + 1}V_{DS + 2}V_DS²

where ₀, ₁ and ₂ are fitting parameters depending on the gate capacity and the radius and helicity of the CNT. As an example, for a gate capacity of 17pF/m and a radius CNT of 3nm ₀ =0.31,

An SWCNT (Single Wall CNT) can act as either a conductor or semiconductor depending on the angle of the atom arrangement along the tube. This is referred to as the chirality vector and is represented by integer pair (n, m).

Fig.4: Construction of grapheme sheet and important parameters for CNTs. C_h is chiral vector, T is tube axis, is chiral angle. [3]

A simple method to determine if a carbon nanotube is metallic or semiconducting is to consider its indices (n, m): the nanotube is metallic if n = m or n-m = 3i, where i is an integer. Otherwise the tube is semiconducting. Every Carbon atom on the sheet can be expressed as a function of integers (n, m). A chiral vector C is the vector perpendicular to the tube axis T, given by

The diameter of CNT can be calculated based on the following equation:

Where a₀ = 0.142nm is the inter-atomic distance between each carbon atoms and its neighbor.

Fig.5: Equivalent circuit model for the intrinsic channel region of a CNTFET [17]-[19]

The threshold voltage is defined the voltage required to turn on the transistor, and the threshold voltage of the intrinsic CNT channel can be approximated to the first order of half bandgap, which is the inverse function of diameter.

From equation (3) it is observed that threshold voltage of CNTFET is inversely proportional to chirality vector of CNT [10].

Quantum capacitance (C_Q) was first introduced by S.Luryi [20], which is associated with the property of channel material. C_Q physically originates in the Fermi level (E_f) penetration into conduction band. The inversion layer of channel in MOSFET devices can be represented as a series of quantum capacitance C_Q and Cetroid capacitance (C_cent) The Centroid capacitance is related to the finite average distance of the electron channel from the insulator/and channel interface[21].

With the decrease in thickness of insulator, the insulator capacitance becomes comparable to the inversion layer capacitance and thus implies that the quantum capacitance and centroid capacitance start to impact the gate capacitance. If all the charges are assumed to be located at the same position inside semiconductor layer, centroid capacitance is not considered. Induced channel charge in a MOS structure actually needed to deliver an amount of energy equal to {Qs²/Cins + Qs²/2Cq} to MOS where, Q_s is total electron charge in channel. The first term is related to the required energy for the electric field in the oxide layer and the second term corresponds to the required energy in the semiconductor layer which occurs due to finite density of state of the semiconductor. Normally C_ins is much smaller than C_Q. So the second term is considered negligible but as device scaling approaches a few nanometers, C_ins becomes very much comparable to or even bigger than C_Q, and C_Q should be carefully considered in these scaled down devices.

From the analysis and simulation [22] it was observed that Quantum capacitance varies with gate Voltage for different oxide thickness in CNTFET.

Fig.4: Bar diagram: Quantum capacitance Vs Gate Voltage with varying oxide thickness

Multilayer perception (MLP)[23] is the most popularly used neural network structure shown in figure (5) . The network consists of an input layer, an output layer and one or more hidden layer(s). A typical neural network structure has two types of basic components, namely, neurons and the link between them. Every link has a corresponding weight coefficient associated to it. Each neuron is defined by a set of inputs, bias coefficient and an activation function. Simply, the output of the neuron can be computed through the equation (8):

Where A is the neuron activation function, W is coefficient associated with the input link, I is the input carried across the link and b is the bias coefficient associated with the neuron.

The training algorithm should be executed in order to specify the weight and bias coefficient [24]. This training algorithm consists of two parts through the different layer of network: forward and backward path.

Figure 6: Basic structure of MLP NN [2]

In the forward path, the input data is applied to the input neurons of the network, and its effect propagates through the network layer by layer. Then a group of outputs is produced as an actual response of the network. The actual response of the output layer is subtracted absolutely from an expected response to produce an error signal. This error signal is then propagated backward through the network, in the opposite direction. During the forward path, the weight and bias coefficients of the networks are not changed while, during the backward path, the coefficients are altered in accordance with an error-correction rule [25]. This error-correction rule can be called the network optimization technique. This process should be repeated several times in order to minimize the error. Each run of a complete set is called an epoch.

Although we have discussed in the paper so many advantages of CNTFETs over MOSFETs but designing a circuit using CNTFET involves trade-offs between different aspects. In particular, we suggest the following aspects as a continuation of this work:

• More experiments need to be done to guarantee the yield of CNTs growth.

• In this paper, we have observed how Threshold voltage of CNTFET based device depends upon chirality vector and diameter. More fabricated devices are needed for statistical analysis and the dependence on contact metal, dielectric thickness would be measured interests. These measurements will help to justify the proposed theories on CNTFETs which will in turn serve fabrication guidelines.

• Several fabrication steps may be improved. For example, SiO2 is used as the substrate to grow nanotubes. Yet using other materials such as polymers won’t change the fabrication flow but may help CNTs and metals stick better to the device. Using those materials might save one e-beam lithography step. It is also possible to transfer the whole fabrication process to clean rooms of higher rating. In e-beam deposition, a clean environment will improve the quality of device rating.

• Some of the proposal ideas are not fully implemented due to lack equipment.

• If a mature fabrication flow is available, future work can focus on device variation characterization,

threshold voltage engineering and noise analysis.

In this paper we have concluded that in nanoscale regime, CNTFET devices are advantageous over MOSFET due to lesser and lesser quantum capacitance, while in case of MOSFET the value of quantum capacitance goes on increasing which leads to increased propagation delay and hence performance degradation. We have also introduce an approach to model the CNTFET using neural network which is well compatible for any analog simulator due to its simple, continuous and derivable equations it is also scalable and can fit the effect of channel length variation. Although CNTFET has been grown in several forms its use is still limited as compare to other widespread technologies, this is mainly due to: 1.) It is still difficult to exactly control CNT growth into desired forms and 2.) CNT growth is still very expensive due to the low yield of CNTs that meet desired geometrical specification.

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Fig.1: CNTFET structure, similar to that of MOSFET