In the CMOS gate given below derive a a test to detect the w

In the CMOS gate given below derive:
(a) a test to detect the wire marked with an X open
(b) a test to detect the PFET driven by input A stuck-on such that gate output voltage deviates maximally from the fault free output voltage
(c) a test to detect the NFET driven by input D stuck-open

Solution

ANSWER:

A. Initially, A,B,C,D,E,F = 1. Then change B, C, E to 0. If it was not faulty, we expect the output to go from logic 0 to logic 1. When there is a fault of this kind, the output will remain at 0.

B. Initially, A, C, E are zero and the rest inputs are at 1. Then, E,D,F are made 1 and the rest remain at 0. When there is a fault present, the voltage level at the output is higher than the value if there was no faulty path.

C. Initially, all inputs are at 0. Then C, D are made to 1 and the rest remain at 0. In the non-faulty case, it is expected that the output voltage goes to logic 0. But, due to a fault, it remains at logic 1 (previous logic level).