My teacher wants us to implement a full adder on verilog He

My teacher wants us to implement a full adder on verilog. He says that if you see the truth table 4 combination results in an output of 1 for each S and Count. This is confusing because a full adder only has 3 inputs. What did he mean by this?

Solution

Actually, what your teacher meant was that the value of S can be 1 for 4 different combinations of the 3 inputs. If you look at the truth table, the value of S is 1 for the combinations:

1) 0 0 1

2) 0 1 0

3) 1 0 0

4) 1 1 1

Similarly the value of Count is 1 for the 4 combinations given below:

1) 0 1 1

2) 1 0 1

3) 1 1 0

4) 1 1 1

Such an information is needed as when you are going to implement the full adder in Verilog, the expressions for S and Count will depend on those values for which they are 1. Thus in this case, all the combinations for which S and count are 1 have to be considered.