An output pad contains a chain of successively larger invert

An output pad contains a chain of successively larger inverters to drive the (relative) enormous off-chip capacitance. If the first inverter in the chain has an input capacitance of 20fF and the off-chip load is 10pF, how many inverters should be drive the load with least delay? Estimate this delay, expressed in the number of FO4 inverter delays.

Solution

A)The method of logical effort is founded on a simple model of the delay through a single mos logic gate.1 The model describes delays caused by the capacitive load that the logic gate drives and by the topology of the logic gate. Clearly, as the load increases, the delay increases, but delay also depends on the logic function of the gate. Inverters, the simplest logic gates, drive loads best and are often used as amplifiers to drive large capacitances. Logic gates that compute other functions require more transistors, some of which are connected in series, making them poorer than inverters at driving current. Thus a nand gate has more delay than an inverter with similar transistor sizes that drives the same load. The method of logical effort quantifies these effects to simplify delay analysis for individual logic gates and multistage logic networks.

The first step in modeling delays is to isolate the effects of a particular integrated circuit fabrication process by expressing all delays in terms of a basic delay unit particular to that process.2 is the delay of an inverter driving an identical inverter with no parasitics. Thus we express absolute delay as the product of a unitless delay of the gate d and the delay unit that characterizes a given process: dabs = d (1.1) Unless otherwise indicat

Unless otherwise indicated, we will measure all times in units of . In a typical 0.6µ process is about 50 ps. This and other typical process parameters are summarized in Appendix B. The delay incurred by a logic gate is comprised of two components, a fixed part called the parasitic delay p and a part that is proportional to the load on the gate’s output, called the effort delay or stage effort f . (Appendix A lists all of the notation used in this book.) The total delay, measured in units of , is the sum of the effort and parasitic delays:

The effort delay depends on the load and on properties of the logic gate driving the load. We introduce two related terms for these effects: the logical effort g captures properties of the logic gate, while the electrical effort h characterizes the load. The effort delay of the logic gate is the product of these two factors:

The logical effort g captures the effect of the logic gate’s topology on its ability to produce output current. It is independent of the size of the transistors in the circuit. The electrical effort h describes how the electrical environment of the logic gate affects performance and how the size of the transistors in the gate determines its load-driving capability.

This equation shows that logical effort g and electrical effort h both contribute to delay in the same way. This formulation separates , g, h, and p, the four contributions to delay. The process parameter represents the speed of the basic transistors. The parasitic delay p expresses the intrinsic delay of the gate due to its own internal capacitance, which is largely independent of the size of the transistors in the logic gate. The electrical effort, h, combines the effects of external load, which establishes Cout, with the sizes of the transistors in the logic gate, which establish Cin. The logical effort g expresses the effects of circuit topology on the delay free of considerations of loading or transistor size. Logical effort is useful because it depends only on circuit topology