Design a circuit that takes as input a four bit word and pro

Design a circuit that takes as input a four bit word and produces as its output an unsigned binary number indicating the length of the longest sequence of consecutive Is in the word. For example, if the input word is 1011, the longest sequence of consecutive 1s is of length 2. Be sure to show truth tables, K-maps (with circlings), and reduced equations. Describe your circuit using a Verilog behavioral dataflow description and simulate it by writing a testbench. Assume the device has a propagation delay of 5 time units. Your solution should employ sum of products form. You can compile and simulate your Verilog program using the Verilogger software system, Mentor Questa/ModelSim or any other Verilog environment. Save and print the timing diagram so that you can include it in your final report. After you get your behavioral dataflow model working and verified, create a Verilog structural description for the same design and verify it. You may use any of the actual logic gates in the 74HCT family. Model your design using actual 74HCT family propagation delay values for the devices you chose. This means that your Verilog program must assign t_pLH and t_PHL values to every gate. You can get these from the 74HCT data sheets, found on the Texas Instruments web site (www.ti.com) - click on \"Logic\" under Find Products. Some are also available via links on the course page. Note that this means that your total propagation delay will be determined by actual devices and will differ from the dataflow design you did. You do not need to use SOP form for the structural description, but if the logic you implement for the structural description differs from the equations you obtained for the dataflow model, you need to show how you derived them. You can use the same testbench that you used to verify your dataflow description (though you may need to change the timing).

Solution

ANSWER:

I will answer shortly.