Assume that a and y are 8bit signals with the stdlogicvector

Assume that a and y are 8-bit signals with the std_logic_vector(7 downto 0) data type. the signals are interpreted as unsigned numbers, the following assignment statement performs a/8. Explain. y \"1001\" \"0110\" > \"0001001\" 2#1010# > \"1010\" 1010 > \"1010\" Repeat Problem 3.8. but assume that the data type is unsigned. Repeat Problem 3.8. but assume that the data type is signed. The. following Signal assignment is syntactically correct. If not.

Solution

3.6)

the signal assignment statement performs the right shift operation by 3. its equivalent to by 8.

for example, consider the number a=64 which divide by 8 will result y=8

a=64=(01000000)₂

y is nothing but a right shift of \'a\' by 3 times

y=(00001000)₂=8, so we got the correct output.

3.7)To get mod 8 value we need to perform the bitwise AND operation with 00000111

y<=\"00000111\"&a

for example, let consider a=65, the equivalent binary value is a=01000001

\"00000111\"&\"01000001\"=00000001