Write a VHDL module to design an 8 bit shift is described as

Write a VHDL module to design an 8 bit shift is described as follows: It has 8- bit input 8- bit output Q, an active low asynchronous reset, a clock and two control bits S1S2. It has additional two inputs LSI (left serial input) and RSI (right serial input) The functional operation of the shift register is given below |(b) Two shift registers (of the type describe in a) are connected to form a 16-bit cyclic shift register which are controlled by bits L and R. If L =1 and R =&~then the 16-bit register is cycled left. If L=0 and R = 1, the register is cycled right. If L= R =1, the 16-bit register is loaded from input vector X (16 bits), otherwise, the content of the register stays the same. Write a structural VHDL description using the module from.

Solution

library ieee;
use ieee.std_logic_1164.all;

entity ShiftReg is
port(clock,rst, s1,s2,LSI,RSI : in std_logic;
D : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0));
end ShiftReg;
architecture archi of ShiftReg is
signal Q: std_logic_vector(7 downto 0);
signal temp: std_logic_vector(7 downto 0);
// 4 to 1 MUX
Process(s1,s2,Q,LSI,RSI)
variable temp : std_logic; // variable declaration
Begin
case S is
when \"00\" => temp:=Q; // stays same
when \"01\" => temp:= Q(6 downto 0)&RSI;// Left shift
when \"10\" => temp:=LSI&Q(7 downto 0);// Right Shift
when Others => temp:=D;// Load D
end case;
end Process;

// Sequential Element

begin
process (C,rst)
begin
if(falling_edge(rst)) then
       Q<=\'0;
else
if (falling_edge(clock)) then
Q<=temp;
end if;
end process;
end archi;

Question 2

library ieee;
use ieee.std_logic_1164.all;

entity CyclicReg is
port(clock,rst,L,R : in std_logic;
D : in std_logic_vector(15 downto 0);
Q : out std_logic_vector(15 downto 0));
end CyclicReg;
architecture archi of CyclicReg is
signal Q: std_logic_vector(7 downto 0);
signal temp: std_logic_vector(7 downto 0);
signal s1,s2,LSI1,LSI2,RSI1,RSI2: std_logic;
signal D1,D2,Q1,Q2: std_logic_vector(7 downto 0);
SFR1: entity ShiftReg port map(clock,s1,s2,LSI1,RSI1,D1,Q1);
SFR2: entity ShiftReg port map(clock,s1,s2,LSI2,RSI2,D2,Q2);
// Combinatorial Block to specify the register interconnections
Process
begin
LSI1 <= Q2(0); RSI1<=Q2(7);
LSI2 <= Q1(0);RSI2 <= Q1(0);
s1 <=L;
s2 <=R;
end Process