Complete Part B Part A is given as a reference Use magnitude

Complete Part B. Part A is given as a reference.

Use magnitude comparators and logic to design a circuit that computes the minimum of three 4-bit numbers.

A. Draw the circuit diagram for the system using 4-bit magnitude comparators.

B. Write the VHDL code for the circuit using the Mag_Comp_4Bit module from the lecture notes. Note, the VHDL keyword “open” can be used in the port map of an instantiated component when an output port is not used and thus not connected to a signal. Leaving the mapped signal blank would result in a syntax error.

Solution

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_arith.all ;
ENTITY mini_3_4bit IS
PORT ( A, B ,C: IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
min_A, min_B, min_C: OUT std_logic) ;
END mini_3_4bit;
ARCHITECTURE Behavior OF mini_3_4bit IS
Component Mag_Comp_4Bit
PORT ( A, B : IN STD_LOGIC_vector(3 DOWNTO 0) ;
AeqB, AgtB, AltB : OUT STD_LOGIC ) ;
END Component ;
signal aec,agc,alc,bec,bgc,blc,aeb,agb,alb:std_logic;
BEGIN
comp1:Mag_Comp_4Bit port map(A,C,aec,agc,alc);
comp2:Mag_Comp_4Bit port map(B,C,bec,bgc,blc);
comp3:Mag_Comp_4Bit port map(A,B,aeb,agb,alb);

min_A<=(alc and alb) or (alc and bec) ;
min_B<=(blc and agb) or (aec and blc);
min_c<=(agc and bgc) or (aec and bgc) or (bec and agc);
END Behavior ;
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_arith.all ;
ENTITY Mag_Comp_4Bit IS
PORT ( A, B : IN STD_LOGIC_vector(3 DOWNTO 0) ;
AeqB, AgtB, AltB : OUT STD_LOGIC ) ;
END Mag_Comp_4Bit;
ARCHITECTURE Behavior OF Mag_Comp_4Bit IS
begin
AgtB<= \'1\' when (A > B)
else \'0\';
AeqB <= \'1\' when (A = B)
else \'0\';
AltB <= \'1\' when (A < B)
else \'0\';
END Behavior ;