how would I write a VHDL code to realize the operation for t

how would I write a VHDL code to realize the operation for the shift register and the defined function table in the pic below. the shift register has a parallel load feature in addition to serial input, Ds. when data is shifted in via Ds,that data will propagate through the shift register beginning with the internal FF Q0 and then Q1 until the data subsequently reach the only 2 physical outputs Q7 and not Q7 .                              

Solution

entity multifunctionshift is
Port ( D : in STD_LOGIC_VECTOR (7 downto 0);
CLK, RST : in STD_LOGIC;
SIR, SIL : in STD_LOGIC;
S :in STD_LOGIC_VECTOR (1 downto 0);
Q : out STD_LOGIC_VECTOR (3 downto 0));
end multifunctionshift;

architecture Behavioral of multifunctionshift is
begin

process(CLK, RST) is
variable REG : std_logic_vector(7 downto 0);
begin
if (RST = \'0\') then
REG := (others => \'0\');
elsif rising_edge(clk) then
case S is
when \"00\"=>REG := D;
when \"01\" =>REG := SIR & REG(3 downto 1);
when \"10\" =>REG := REG(2 downto 0) & SIL;
when others=>REG:= REG(0)& REG(3 downto 1);
end case;
end if;
Q <= REG;
end process;
end Behavioral;