Write a VHDL stdlogic code description for a counter 7 1 2 5

Write a VHDL std_logic code description for a counter 7, 1, 2, 5 then repeat, entity part 1 is Port (clk: in std logic; Q: out std logic vector (2 downto 0)) end part 1; architecture Behavioral of part 1 is Type state type is (one two five seven); Signal state: state type. begin process begin if then CASE state IS when state Q state

Solution

process(clk)

begin

if clk \'event clk=1 then

case state is

when seven=>

state<=one;Q<=001;

when one=>

state<=two;Q<=010;

when two=>

state<=five;Q<=101;

when five=>

state<=seven;Q<=111;