Homework SourseA smart home control module with 8 switches and associated r
A smart home control module with 8 switches and associated registers is connected as an input device through an I/O interface board to the MC68HC11 microcontroller. After the microcontroller requests to perform a READ operation on the smart home control module, the ON/OFF status of each switch (S0 – S7) denoted as 1/0 will be updated to the data buffer register (DBR) of the I/O interface board. S7 will be loaded into the MSB (bit 7) of DBR while S0 will be loaded into its LSB (bit 0) during each update. For instance, if S7 is ON while the remaining switches (S0 – 6) are OFF, the updated content of DBR should be: 100000002. For any input device, the control/status register (CSR) and DBR of the I/O interface board is assigned to memory address $8004 and $8006 respectively. The command code to perform a READ operation on the smart home control module is $28.
1.Clearly explain the detailed steps with an illustrative diagram to load 1 byte of data from the DBR of the I/O interface board to the Accumulator B of the MC68HC11 microcontroller using the programmed I/O mechanism.
2.Assume switches S7, S5, S4 and S2 are ON and the remaining are OFF at the moment, after applying the programmed I/O mechanism described in (1), what are the resulting contents of Accumulator A and B?
Solution
P =PI + P2
The \"5\" in the part number highlighted the fact that the 8085 uses a single +5-volt (V) power supply by using depletion-modetransistors, rather than requiring the +5 V, 5 V and +12 V supplies needed by the 8080. This brought it up with the competing Z80, a popular 8080-derived CPU introduced the year before. These processors could be used in computers running the CP/M operating system.
The 8085 is supplied in a 40-pin DIP package. To maximise the functions on the available pins, the 8085 uses a multiplexed address/data bus. However, an 8085 circuit requires an 8-bit address latch, so Intel manufactured several support chips with an address latch built in. These include the 8755, with an address latch, 2 KB of EPROM and 16 I/O pins, and the 8155 with 256 bytes of RAM, 22 I/O pins and a 14-bit programmable timer/counter. The multiplexed address/data bus reduced the number of PCB tracks between the 8085 and such memory and I/O chips.
