Model the following parallel addersubtracted circuit using s

Model the following parallel adder/subtracted circuit using structural VHDL. All instantiated components must be fully defined.

Solution

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity adder_subtractor_16bit is
    port(
        a : in STD_LOGIC_VECTOR(15 downto 0);
        b : in STD_LOGIC_VECTOR(15 downto 0);
        sel : in STD_LOGIC;
        sum : out STD_LOGIC_VECTOR(15 downto 0)
         );
end adder_subtractor_16bit;

architecture adder_16bit_arc of adder_subtractor_16bit is

Component fa is
    port (a : in STD_LOGIC;
          b : in STD_LOGIC;
        c : in STD_LOGIC;
        sum : out STD_LOGIC;
        carry : out STD_LOGIC
        );
end component;        

signal s : std_logic_vector (15 downto 0);
signal l : std_logic_vector (15 downto 0);


begin         
    
    l <= b xor (sel & sel & sel & sel);
    
O0 : fa port map (a(0),B(0),sel,sum(0),s(0));
O1 : fa port map (a(1),B(1),s(0),sum(1),s(1));
O2 : fa port map (a(2),B(2),s(1),sum(2),s(2));
O15 : fa port map (a(15),B(15),s(14),sum(15),open);

end adder_16bit_arc;