For the TTL inverter shown above calculate the propagation d

For the TTL inverter shown above calculate the propagation delay tp using tphl and tplth. Vdd = 5V. B = 100.

Solution

The propagation delay time for a gate is the time required for the output to respond to a change
in an input. In all practical gates, a time lag exists between an input change and the
corresponding output response. The time interval between the instants when the input and output
change states is not a satisfactory measure of the delay time of a logical device for two reasons.
First, the input signals to gates and the output signals produced by gates are not the idealized
pulses studied in theory. Figure 3.4 illustrates the nonideal input and output signals to a NAND
gate. The transitions between HIGH and LOW voltage levels have nonzero rise and fall times.
The time required for a signal to rise from 10% to 90% of its final value is called the rise time, tr.

The average propagation delay time tp is then defined by: