Using Verilog design a mod60 BCD counter that performs a cou

Using Verilog, design a mod-60 BCD counter that performs a counting sequence: BCD1BCD0 = 00, 01, 02, 03, 04, 05, ..., 57, 58, 59,00, 01, 02, 03, 04, 05, 06, .... The counter should have a Clear input which asynchronously clears the outputs to 00. Using Verilog, modify the code from Problem 1 so that the BCD counter is now a mod-24 one (counting range from 0 to 23). Some additional if-else statements and logical operators might be required.

Solution

verilog code for Mod 60:

module mod60 ( clk ,clear ,BCD1,BCD0 );

output reg [3:0] BCD1 ;
output reg [3:0] BCD0 ;
reg [7:0] dout ;
input clk ;
wire clk ;
input clear ;
wire clear ;

initial dout = 0 ;

always @ (posedge (clk)) begin
if (clear)
dout <= 0;
else if (dout<=59) begin
dout <= dout + 1;
end

else if (dout==60)

begin
dout <= 0;
end
BCD1=dout[7:4];
BCD0=dout[3:0];
end

endmodule

for mod-24:

verilog code for Mod 60:

module mod60 ( clk ,clear ,BCD1,BCD0 );

output reg [3:0] BCD1 ;
output reg [3:0] BCD0 ;
reg [7:0] dout ;
input clk ;
wire clk ;
input clear ;
wire clear ;

initial dout = 0 ;

always @ (posedge (clk)) begin
if (clear)
dout <= 0;
else if (dout<24) begin
dout <= dout + 1;
end

else if (dout==24) begin
dout <= 0;
end
BCD1=dout[7:4];
BCD0=dout[3:0];
end

endmodule