Consider the following characteristics of a cache memory sys

Consider the following characteristics of a cache memory system: Addresses are 32-bits. The memory is byte addressable. The CPU accesses 4-byte words. Blocks have 64 bytes. The cache is 8-way set associative with 1024 sets. Which one of the following shows the address breakdown for an efficient cache implementation having the characteristics above?

Solution

The answer is E

because the symbol of set associative mapping is -> TAg     set       word

where t->tag, s-> set ,b ->word

In E we have 4 byte words represented by b bits, we have total address as 32 bitsMoreoever we have total tag bits as 8 from 24 to 32.This shows it is 8 way set associative.The blocks have 64 bytes here