I am trying to do a bit counter that only counters bits of 1

I am trying to do a bit counter that only counters bits of \'\'1\'\' and not \'\'0\'\'

Here is my code, but it does not work :/

can somebody please give me a hand?

i HAVE to use loop statements.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;

entity Ones_counter is
port(
ONES_IN: in std_logic_vector(7 downto 0);
ONES_OUT: out std_logic
);
end Ones_counter;

architecture behav_sig of Ones_counter is
begin
test_case: process (ONES_IN)
   variable counter :std_logic;
   begin
   counter := 0;-- Counter set to 0
       for index in 7 downto 0 loop
           if (ONES_IN(index) = \'1\')
               then counter :=counter + 1;
           end if;
       end loop;
       ONES_OUT <= counter;
end process test_case;
end behav_sig;

Solution

Since your input is 8-bit wide. It is possible that all bits may set from all ‘0’ to all ‘1’. Thus counter value and output ONES_OUT must be 4-bit wide.

Corrections are :-

ONES_OUT : std_logic_vector (3 downto 0);

Counter : std_logic_vector (3 downto 0);