3bit Adder with BCDSeven Segment Display Decoder PreLab Pact

3-bit Adder with BCD/Seven Segment Display Decoder

Pre-Lab Pact A BCD-to-seven-segment decoder is a combinational circuit that converts a decimal digit in BCD to an appropriate code for the selection of segments in an indicator used to display the decimal digit in a familiar form. The seven outputs of the decoder (a b, e, d e. J g) select the corresponding LEDs in the display, as shown in figure below. The numeric display chosen to represent the decimal digit is shown as well. (a) Segment designation (b) Numerical designation for display Write the truth table relating the four binary inputs to the 7 LED outputs of the BCD-to-seven-segment decoder. DO NOT use K-M essions. Draft the Verilog code using behavioral it seven-segment representation. faps. There\'s no need for logic expr modeling. Use a Case Statement relating the binary number input to i Part 2 Draft the arithmetic statement (in Dataflow or Behavioral) for a 3-bit adder. Don\'t forget to properly define the input and sum registers.

Solution

ANSWER:

Part - 1:

Let the 4-bit input be denoted as A₃A₂A₁A_0. Following will be the truth table.

VERILOG CODE:

`define Z 1\'b0

`define O 1\'b1

case ({A3,A2,A1,A0}) :

4\'h0 : assign {a,b,c,d,e,f,g} = {O,O,O,O,O,O,Z};

4\'h1 : assign {a,b,c,d,e,f,g} = {Z,O,O,Z,Z,Z,Z};

4\'h2 : assign {a,b,c,d,e,f,g} = {O,O,Z,O,O,Z,O};

...........

4\'hf : assign {a,b,c,d,e,f,g} = {Z,Z,Z,Z,Z,Z,Z};

endcase

PART 2:

module 3b_adder (input bit [2:0] A, input bit [2:0] B, output bit [2:0] sum, output bit carry);

assign {carry, sum} = A + B;

endmodule

A3	A2	A1	A0	a	b	c	d	e	f	g
0	0	0	0	1	1	1	1	1	1	0
0	0	0	1	0	1	1	0	0	0	0
0	0	1	0	1	1	0	1	1	0	1
0	0	1	1	1	1	1	1	0	0	1
0	1	0	0	0	1	1	0	0	1	1
0	1	0	1	1	0	1	1	0	1	1
0	1	1	0	1	0	1	1	1	1	1
0	1	1	1	1	1	1	0	0	0	0
1	0	0	0	1	1	1	1	1	1	1
1	0	0	1	1	1	1	1	0	1	1
1	0	1	0	0	0	0	0	0	0	0
1	0	1	1	0	0	0	0	0	0	0
1	1	0	0	0	0	0	0	0	0	0
1	1	0	1	0	0	0	0	0	0	0
1	1	1	0	0	0	0	0	0	0	0
1	1	1	1	0	0	0	0	0	0	0