5 Assume that control signals are deasserted when 0 and asse

5. Assume that control signals are deasserted when 0 and asserted when 1. Consider the items listed below

I. 9
II. 16
III. 32
IV. zero bits
V. pipeline bubble
VI. nop

a) (10) For each of the three blanks (1) through (3) within the following statement, select one of the above terms I through VI to fill-in the each blank ( a different item for each blank):

The assemble generates __(1)____ __(2)___ to create a __(3)_______.

b) (10) For each of the three blanks (1) through (3) within the following statement, select one of the above terms I through VI to fill-in the each blank ( a different item for each blank):

The control unit generates __(1)____ __(2)___ to create a __(3)_______.

Solution

I) The Assemble generates 1) 16 (2) 32 to create (3) nop........

2) The Control Unit Generates (1) zero bits (2) 9 to create a (3) pipeline bubble