Write the Verilog code for a 4 bit D flip flop with synchron

Write the Verilog code for a 4 bit D flip flop with synchronous reset. Write the Verilog code for the same 4 bit D flip flop with asynchronous reset.

Solution

(a)

module d_ff (
input clk,d,rst_n,
output reg q);
always@(posedge clk )
    begin
        if (!rst_n)
            q <= 1\'b0;
        else
            q <= d;
    end

endmodule

(b)

library IEEE;

use IEEE.std_logic_1164.all;

entity dff_async_rst is

port( data, clk, reset: in std_logic;

q: out std_logic);

end dff_async_rst;
architecture behav of dff_async_rst is

begin

process(clk,reset)

begin

if (reset=’0’) then

q<=’0’;

elsif (clk’event and clk=’1’) then

q<=data;

end if;

end process;

end behav;