Write a Verilog program using data flow modeling or gateleve

Write a Verilog program using data flow modeling or gate-level modeling for the function in number 2. F = ABC bar + A B bar

Solution

using Gate level modeling:

module function2(F,A,B,C);
output F;
input A,B,C;
wire b,c,D,E;
not
ua1(b,B),
ua2(c,C);
and
ub1(D,A,B,c),
ub2(E,A,b);
or
uc(F,D,E);
endmodule