We are dealing with Verilog language What is a major design

We are dealing with Verilog language.......

What is a major design advantage when using a ripple counter?

Design simplicity.

Glitch free.

High speed.

Outputs are all synchronized.

Solution

advantages of design of asynchronous(ripple) counter in verilog code are

1.Removes reset from the data path.

2.multi clock systems needs only one reset.

3.Faster in speed.

So answer is (c)