Please show your Xilinix code Create a 3bit finite state mac

****Please show your Xilinix code.

Create a 3-bit finite state machine that counts up, down, and cycles through 2 sets of gray code. It will have a reset and run on a 50MHz clock. The 2-bit input will be called x, and the 3-bit output will be called myoutputs. Here is how it will operate:

Solution

module fsm( clk, rst, inp, outp); input clk, rst, inp; output outp; reg [3:0] state; reg outp; always @( posedge clk, posedge rst ) begin if( rst ) state <= 00; else begin case:( state 00 ) begin if( inp00 ) state <= 000; else state <= 001; else state <= 010; else state <= 011; else state <= 100; else state <= 101; else state <= 110; else state <= 111; end; State01: begin if( inp01 ) state <= 000; else state <= 111; else state <= 110; else state <= 101; else state <= 100; else state <= 011; else state <= 010; else state <= 001; end; state10: begin if( inp10 ) state <= 000; else state <= 010; else state <= 110; else state <= 100; else state <= 101; else state <= 111; else state <= 011; else state <= 001; end; state11: begin if( inp11 ) state <= 000; else state <= 100; else state <= 101; else state <= 111; else state <= 110; else state <= 010; else state <= 011; else state <= 001; end; endcase; end; end; always @(posedge clk, posedge rst) begin if( rst ) outp <= 0; else if( state == 11 ) outp <= 1; else outp <= 0; end; endmodule;