For the synchronous circuit below CLK input not shown Find t

For the synchronous circuit below (CLK input not shown): Find the maximum operating frequency and the time at which output Z becomes usable after the active edge of the clock. Consider only the following paths: Path 1: Input X, OR gate, flip-flop 1. Path 2: Output Ql, XOR gate, flip-flop 0. Assume the following delays:

Solution

a) Maximum Operating Frequency:

f_max = 1/maximum delay(critical path delay).

for the given circuit and delay values the path with maximum delay is Path-1 because

path-1 delay = T_pd(X) + T_pd (OR) + T_su + T_pd (Flip-flop) = 14+8+10+7 = 39 nsec

path-2 delay = T_pd (Flip-flop) + T_pd (XOR) + T_su = 7+20+10 = 37 nsec

Therefore maximum operating frequency = 1/39nsec = 25.641 MHz.

b) Output Z i dependent on only Q1 and Q0.

so the delay from clock edge to output Z is equal to T_pd (Flip-flop) +T_pd (AND) = 7+9 = 16nsec.

i.e After 16nsec after clock active edge output is usable.