Writing Verilog Just need something to get started Create a

Writing Verilog

Just need something to get started.

Create a library of parameterized datapath components and use synthesis results from that library to estimate the critical path for various circuits specified using a behavioral netlist. Finally, compare the estimated critical path to actual critical path by implement the circuits using Verilog and and synthesizing the circuit. Verilog implementation of Datapath Component Library Create parameterized Verilog implementations of the following datapath components. Each component should be modeled using a single Verilog module. Each module should include a Verilog parameter named datawidth that specifies the number of bits for the data inputs and outputs. The following provides an overview of the required components for all students:

Solution

Register DFF

module DFF( clk, rst, d, q)

input clk;

input rst;

input d;

output q;

if clk==1;

assign d ==q;

endmodule

Adder

module adder (a, b,cin, sum,carry)

input a, b;

output cin;

assign sum= a+b

assign cin =a xor b

endmodule

subtractor

module subtractor( a, b, c, diff, borr)

input a, b;

assign diff = a^b^c;

assign borr= (~a)&b | (~b)&c|(~c)&a)

endmodule

Multiplier

module multiplier (a,b, out)

input a,b;

out = a*b;

endmodule

coparator

module coparator( a,b, L,G,E,out)

input a,b;

output L,G,E,out ;

if a>b, assign out = G;

else L;

if a<b, assign out=L;

else G;

if a==b, assign out =E;

endmodule

MUX

module MUX2:1

input a,b,sel[0:1];

tmp =out;

output d;

if sel[0:0], out=b;

else out= a;

assign d=a+b;

endmodule

shift_right

module shift_right ( a, asrt,d)

input a, asrt;

output d;

if a = a++, assign a= asrt

else a =a;

endmodule

shift left

module shift_left( a, aslft,d)

input a, aslft;

output d;

if a = a--, assign a = aslft

else a=a;

endmodule