A Consider a comparator with two 8bit inputs a and b The a a

A)

Consider a comparator with two 8-bit inputs, a and b. The a and b are with the

std_logic_vector data type and are interpreted as unsigned integers. The comparator

has an output, agtb, which is asserted when a is greater than b. Assume that only a single bit

comparator is supported by synthesis software. Derive the circuit with concurrent signal

assignment statements

B)

repeat but assume that a and b are interpreted as signed integers

Solution

In an 8-bit comparator, the input size of an operand (i.e., n) is 8. The circuit have 16 inputs and three outputs.

a)

library ieee;
use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned all;
entity comp8 is
port(
a,b: in std_logic_vector(7 downto 0);
Agtb, Aeqb, Altb: out std_logic
);
end comp8;
architecture bit8_Comparator of comp8 is
signal e1,e0,s1,s0,l1,l0: std_logic;
begin
comp1_unit: entity work.comp4(bit4_Comparator)
port map(a(3)=>a(7), a(2)=>a(6), a(1)=>a(5), a(0)=>a(4), b(3)=>b(7), b(2)=>b(6), b(1)=>b(5), b(0)=>b(4), Altb=>e1, Aeqb=>s1, Agtb=>l1 );
comp2_unit: entity work.comp4(bit4_Comparator)
port map(a(3)=>a(3), a(2)=>a(2), a(1)=>a(1), a(0)=>a(0), b(3)=>b(3), b(2)=>b(2), b(1)=>b(1), b(0)=>b(0), Altb=>e0, Aeqb=>s0, Agtb=>l0 );
Altb <= e1 and e0;
Agtb <= l1 or (e1 and l0);
Aeqb <= s1 or (e1 and s0);
end bit8_Comparator;

b) for signed inputs:

library ieee;
use ieee.std_logic_1164.all;

entity comp8 is
port(
a,b: in std_logic_vector(7 downto 0);
Agtb, Aeqb, Altb: out std_logic
);
end comp8;
architecture bit8_Comparator of comp8 is
signal e1,e0,s1,s0,l1,l0: std_logic;
begin
comp1_unit: entity work.comp4(bit4_Comparator)
port map(a(3)=>a(7), a(2)=>a(6), a(1)=>a(5), a(0)=>a(4), b(3)=>b(7), b(2)=>b(6), b(1)=>b(5), b(0)=>b(4), Altb=>e1, Aeqb=>s1, Agtb=>l1 );
comp2_unit: entity work.comp4(bit4_Comparator)
port map(a(3)=>a(3), a(2)=>a(2), a(1)=>a(1), a(0)=>a(0), b(3)=>b(3), b(2)=>b(2), b(1)=>b(1), b(0)=>b(0), Altb=>e0, Aeqb=>s0, Agtb=>l0 );
Altb <= e1 and e0;
Agtb <= l1 or (e1 and l0);
Aeqb <= s1 or (e1 and s0);
end bit8_Comparator;

A) Consider a comparator with two 8-bit inputs, a and b. The a and b are with the std_logic_vector data type and are interpreted as unsigned integers. The compa
A) Consider a comparator with two 8-bit inputs, a and b. The a and b are with the std_logic_vector data type and are interpreted as unsigned integers. The compa

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