The whenelse conditional signal assignment offers an alterna

The \"when/else\" conditional signal assignment offers an alternative to the IF statement. Unlike IF, when/else does not go in a process, so it is quicker to write. Being outside the process it must be kept simple (no nesting for example). The code below makes Z = \"101\" when ADDR = \"01\" or \"10\", Z = \"111\" when ADDR = \"11\" and Z = \"000\" for all other ADDR values (ADDR = \"00\"). Rewrite the VHDL code replacing the \"when/else\" with a IF statement. Just like IF, the \"when/else\" can be handle more complicated expressions than the CASE or \"with/select\". library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity hwl2_p3 is Port (signal ADDR: in STD_LOGIC_VECTOR(1 DOWNTO 0); signal Z out: STD_LOGIC_VECTOR(2 DOWNTO 0)); end hw12_p3; architecture behavioral of hw12_p3 is begin outside all processes Z

Solution

library IEEE;

entity hw12_p3 is

Port( signal ADDR: in STD_LOGIC_VECTOR(1 DOWNTO 0);

signal Z : out STD_LOGIC_VECTOR(2 DOWNTO 0);

end hw12_p3;

architecture behavioral of hw12_p3 is

process(ADDR)

begin

if ( ADDR = \"01\") or (ADDR = \"10\") then

Z<= \"101\";

elsif( ADDR = \"11\") then

Z<= \"111\";

else

Z<= \"000\";

end if;

end process;

end behavioral;