What would the testbench for this code be ENTITY mux41x8bit

What would the testbench for this code be?

ENTITY mux4_1x8bit IS
PORT(i0,i1,i2,i3 : IN BIT_VECTOR(7 downto 0);
       s0,s1 : IN bit;
       r : OUT bit_vector(7 downto 0));
END mux4_1x8bit;

ARCHITECTURE one OF mux4_1x8bit IS
BEGIN
r <= i0 WHEN (s1=\'0\' AND s0=\'0\') ELSE
       i1 WHEN (s1=\'0\' AND s0=\'1\') ELSE
       i2 WHEN (s1=\'1\' AND s0=\'0\') ELSE
       i3;
END one;

Solution

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the rollowing library declaration ir using
-- arithmetic runctions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY tb_mux4_1 IS
END tb_mux4_1;

ARCHITECTURE behavior OF tb_mux4_1 IS

-- Component Declaration ror the Unit Under Test (UUT)

COMPONENT mux4_1
PORT(i0,i1,i2,i3 : IN BIT_VECTOR(7 downto 0);
       s0,s1 : IN bit;
       r : OUT bit_vector(7 downto 0));
END COMPONENT;

--Inputs outputs
signal s0, s1 : std_logic;
signal selectors : std_logic_vector(1 downto 0);
signal i0,i1,i2,i3,r:std_logic_vector(7 downto 0);
begin
mapping: Mux_4_to_1 port map(i0,,i1,i2,i3, s0, s1, r );

--Concurrent processes
process
begin  

s0 <= \'0\'; s1 <= \'0\';wait for 5 ns;
s0 <= \'1\'; s1 <= \'0\';wait for 5 ns;
s0 <= \'0\'; s1 <= \'1\';wait for 5 ns;
s0 <= \'1\'; s1 <= \'1\';wait for 5 ns;
end process;

process(s1, s0)
begin
selectors <= s1&s0;
end process;

process
begin
--TEST 1
i0 <= \'00000000\';
i1 <= \'00000010\';
i2 <= \'00000100\';
i3 <= \'00001000\';
wait for 15 ns;

case selectors is
when \"00\" =>
assert(r = \'00000000\') report \"Error 1: 00\" severity error;
when \"01\" =>
assert(r = \'00000010\') report \"Error 1: 01\" severity error;
when \"10\" =>
assert(r = \'00000100\') report \"Error 1: 10\" severity error;
when \"11\" =>
assert(r = \'00001000\') report \"Error 1: 11\" severity error;
when others =>
assert true;
end case;

--TEST 2
i0 <= \'10000000\';
i1 <= \'01000010\';
i2 <= \'00100100\';
i3 <= \'00011000\';
wait for 15 ns;

case selectors is
when \"00\" =>
assert(r = \'10000000\') report \"Error 1: 00\" severity error;
when \"01\" =>
assert(r = \'01000010\') report \"Error 1: 01\" severity error;
when \"10\" =>
assert(r = \'00100100\') report \"Error 1: 10\" severity error;
when \"11\" =>
assert(r = \'00011000\') report \"Error 1: 11\" severity error;
when others =>
assert true;
end case;

  end process;
end tb;