Write the VHDL code for an 8 bit full adderSolutionlibrary I

Write the VHDL code for an 8 bit full adder

Solution

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity adder8bit is

Port( a: in STD_LOGIC_VECTOR (7 downto 0);

b: in STD_LOGIC_VECTOR (7 downto 0);

cin: in STD_LOGIC;

o: out STD_LOGIC_VECTOR (7 downto 0);

cout: out STD_LOGIC);

end adder8bit;

architecture Behavioral of adder8bit is

component fulladder is

Port ( a :in STD_LOGIC;

b :in STD_LOGIC;

cin :in STD_LOGIC;

o :out STD_LOGIC;

cout: out STD_LOGIC);

end component;

signal c:std_logic_vector(7 downto 1) := (others=>\'0\');

C1: fulladder port map(a=>a(0), b=>b(0), cin=>cin, o=>o(0), cout=>c(1) );

C2: fulladder port map(a=>a(1), b=>b(1), cin=>c(1), o=>o(1), cout=>c(2) );

C3: fulladder port map(a=>a(2), b=>b(2), cin=>c(2), o=>o(2), cout=>c(3) );

C4: fulladder port map(a=>a(3), b=>b(3), cin=>c(3), o=>o(3), cout=>c(4) );

C5: fulladder port map(a=>a(4), b=>b(4), cin=>c(4), o=>o(4), cout=>c(5) );

C6: fulladder port map(a=>a(5), b=>b(5), cin=>c(5), o=>o(5), cout=>c(6) );

C7: fulladder port map(a=>a(6), b=>b(6), cin=>c(6), o=>o(6), cout=>c(7) );

C8: fulladder port map(a=>a(7), b=>b(7), cin=>c(7), o=>o(7), cout=>cout);

end behavioral;