Two submodules partA and partB have been designed as two Ver

Two submodules partA and partB have been designed as two Verilog files partA.v and partB.v, readily available for use. module partA (x, y, d); input x, y; output reg [2:0] d; .... endmodule module partB(w, s); input [2:0] w; output s; ... endmodule The diagram of mycircuit is shown in Fig.2. Write a Verilog file for the top module part of module mycircuit by instantiating modules partA and partB. Use the signal names in the diagram for your Verilog codes.

Solution

module(f,x)

input [1:0] x;

output f;

wire [2:0] t;

partA A(x[1],x[0],t[2],t[1],t[0]);

partB B(t[2],t[1],t[0],f);

end module