Based on the following schematic Write the complete VHDL cod

Based on the following schematic, Write the complete VHDL code set with COMPONENT keyword.

Solution

We can implement the above circuit with following components:

1) 2 input AND gate

2) JK Flip Flop

3) 2 input XOR gate

Implement the above components in VHDL first then write VHDL code in structral modellling for the entire sequentail circuit.

----------------------------------VHDL code for 2 input AND gate--------------------------------------------------

----------------------------------VHDL code for 2 input XOR gate--------------------------------------------------

---------------------------------VHDL code for JK flip flop-------------------------------------------------------------------

library ieee;

use ieee. std_logic_1164.all;

use ieee. std_logic_arith.all;

use ieee. std_logic_unsigned.all;

entity JKFF is

PORT( J,K,Clk: in std_logic;

Q,Q_n+1: out std_logic);

end JKFF;

Architecture behavioral of JKFF is

begin

PROCESS(CLOCK)

variable TMP: std_logic;

begin

if(clk=\'1\' and clk\'event) then

if(J=\'0\' and K=\'0\')then

TMP:=TMP;

elsif(J=\'1\' and K=\'1\')then

TMP:= not TMP;

elsif(J=\'0\' and K=\'1\')then

TMP:=\'0\';

else

TMP:=\'1\';

end if;

end if;

Q<=TMP;

Q_n+1<=not TMP;

end PROCESS;

end behavioral;

----------------------------------VHDL code for Complete circuit in Structural Modelling--------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all

entity seq_ckt is

port ( X, clk: in std_logic;

        Q_0,Q_1:inout std_logic;

         Z: out std_logic);

end entity seq_ckt;

architecture structiral of seq_ckt is

component JKFF is

port (J, K, clk: in std_logic;

        Q : out std_logic);

end component JKFF;

component and2 is

port (a, b, : in std_logic;

        c : out std_logic);

end component and2;

component xor2 is

port (a, b, : in std_logic;

        c : out std_logic);

end component xor2;

signal K_0, K₁, S_0, S₁: std_logic;

Begin

L1: and2 port map (a=>Q_0, b=> Q_1,c=> K₀);

L2: JKFF port map (J=> X, K=> K_0, clk =>clk, Q=>Q_0, Q_n+1=> S₀);

L3: and2 port map (a=>X_, b=> \'1\', c=> K₁);

L4: JKFF port map (J=>X, K=> K_1, clk =>clk, Q=>Q_1, Q_n+1=> S₁);

L5: xor2 port map (a=>X_, b=> Q₁, c=>Z);

end architecture structiral;

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