Q1 20 points Develop a VHDL entity declaration for the seria

Q1. (20 points) Develop a VHDL entity declaration for the serial adder (all ports have to be std_logic and std_logic_vector types).

Q1. Draw the circuit. Implement the serial adder in a structural VHDL. Your description is to be composed of the following five components and a few internal signals (internal descriptions of all components should use “processes”):

Component - 1 bit full_adder,

Component - D - flip flop with enable and asynchronous reset,

Component - 2 inputs AND gate. One of the inputs is to be active low the second one active-high.

Two components which describe 4-bit parallel load shift registers: regA and regB. The functionality of the registers should be similar to 74LS194A – 4-Bit Bi-directional Universal Shift Register.

Note: All registers and flip-flop are rising edge active.

Functional details of the serial adder (Note: for shift registers: 00: hold; and 11: load; and 01: shift right; see below details):

·On the rising edge of a clk signal, when reg_control is ”11”, the registers are loaded with in_a (regA) and in_b (regB). On the rising edges of a clk, when reg_control is ”01”, the registers are shifted (LSB first) into the 1 bit full adder.

·The full adder’s sum bit is shifted into the register port holding the in_a. After 4 clock rising edges, while the reg_control remains ”01”, the regA register contains the value in_a + in_b and carry should be the corresponding carry out bit.

The output sum is assumed not to be valid until the 4th rising edge of a clk signal after load is set to ’0’.

Solution

The entity declaration for serial adder declaring the input and output variables, and architecture description are given below.

entity serial_adder is

    port(in_a: in std_logic_vector(3 downto 0);

         in_b: in std_logic_vector(3 downto 0);

         reg_control: in std_logic_vector(1 downto 0);

clk: in std_logic;

reset_adder: in std_logic;

sum: out std_logic_vector(3 downto 0);

carry: out std_logic);

end entity serial_adder;

architecture arc_serial_adder of serial_adder is

signal c_in,c1,c2,c3 :bit;

begin