7 A 1bit memory cell consists of a latch and a tristate buff

7. A 1-bit memory cell consists of a latch and a tristate buffer, as shown in Figure 3.14 It uses a line for both input and output. When SEL 0, the latch captures the logic level ofthe line at INand transfers itto OUT When SEL-1, the logic value of OUT remains the same regardless of the value on IN. The value at OUT can be connected to the INPUT/OUTPUT line by making T - 1 in the tristate buffer, enabling it. When T = 0, the tristate buffer is disabled and isolates OUT from the INPUT/OUTPUT line. We control the memory cell viatwocontrol lines: ENABLE and READ/WRITE The communications protocol is then the following ·When we wish to communicate with the memory cell we make ENABLE = 0· In When wewant to write to the memorycell, wemake READ/WRITE = 0, When When we want to read the value stored in the memory cell we make addition this occurs, we need to enable the latch and disable the buffer READ/WRITE-1. Then we need to disable the latch and enable the buffer . When we do not want to communicate with the memory cell, we need to disable the buffer but still make sure that the memory remembers its stored value (keeping OUT from changing)

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