A serial data path needs a 1000 ns delay A shift register wi

A serial data path needs a 1000 ns delay. A shift register with serial-in/parallel-out is used for this purpose. Which output from the shift-register above will provide the correct output to extract the serial signal (correct delay)? Assume that the data is presented to the serial inputs right before the rising edge of the clock and also the propagation time of the internal flip-flops is very small. The clock frequency of the shift register is 2MHz

a) Q0

b)Q1

c) Q4

d) None of the above

Solution

Answer is d