Write the VHDL code for the 8input multiplexer shown below u

Write the VHDL code for the 8-input multiplexer shown below using the with select construct: Library ieee; Use leee.std_logic_1164. All; Entity mux is prt std_Logic_Vector(_downto 0); std_logic; std_Logic_Vector(_downto 0);); End mux; Arehitecture are of is begin with select

Solution

library ieee;
use ieee.std_logic_1164.all;

entity mux is
     port(
         input : in STD_LOGIC_VECTOR(3 downto 0);
         sel : in STD_LOGIC_VECTOR(1 downto 0);
         y : out STD_LOGIC
         );
end multiplexer_4_1;

architecture arc of mux is
begin

    with sel select y <=
            din(0) when \"000\",
            din(1) when \"001\",
            din(2) when \"010\",
            din(3) when \"011\",
            din(4) when \"100\"
            din(5) when \"101\"
            din(6) when \"110\"
            din(7) when \"111\"  
            \'-\' when others;

end arc;