hi Im trying to design a circuit where I will try to match t

hi,
I\'m trying to design a circuit where, I will try to match the randomly generated pattern using pins from my FPGA board. I\'m also trying to get the circuit to detect if my pattern and the generated pattern match. if they match, the circuit should generate the next random pattern so that I could try to match it again. if they don\'t, then the circuit outputs 0.

I\'m having difficulties determining how to go about this problem. especially that I want the randomly generated patterns to be slow enough so that I\'m able to keep up with it. Please any suggestions on how I can design this circuit would be very helpful. A block diagram would be very helpful as well.

thank you for helping!

Solution

The CAD tools enable you to design combinational and sequential circuits starting with Verilog

HDL design specifications. The steps of this design procedure are listed below:

1.Create Verilog design input file(s) using template driven editor.

2.compile and implement the Verilog design file(s).

3.Create the testvectors and simulate the design (functional simulation) without using a

PLD (FPGA or CPLD).

4.

Assign input/output pins to implement the design on a target device.

5.

Download bitstream to an FPG

A or CPLD device.

6.

Test design on FPGA/CPLD device

A Verilog input file in the Xilinx software environment consists of the following segments:

Header:

module name, list of input and output ports.

Declarations:

input and output ports, registers an

d wires.

Logic Descriptions:

equations, state machines and logic functions.

End:

endmodule

All your designs for this lab must be specified in the above Verilog input format. Note that the

state diagram

segment does not exist for combinational logic

designs

In this lab digital designs will be implemented in the Basys2 board which has a Xilinx Spartan3E

–

XC3S250E FPGA with CP132 package. This FPGA part belongs to the Spartan family of FPGAs.

These devices come

in a variety of packages.

We will be using devices that are packaged in 132

pin package with the following part number: XC3S250E

-

CP132. This FPGA is a device with about

50K gates.

Xilinx Tools can be started by clicking on the Project Navigator Icon on the Windows desktop.

This should open up the Project Navigator window on your screen.

2-

Select

File

-

>New Project

to create a new project. This will bring up a new pr

oject window

(Figure

2

)

on the desktop. Fill up the necessary entries as follows

Project Name

:

Write the name of your new project

Project Location

:

The

directory where you want to store the new project (Note: DO NOT

specify the project location as a folder on Desktop or a folder in the Xilinx

\\

bin directory.

Your H: drive is the best place to put it.

The project location path is NOT to have any spaces

in

it eg: C:

\\

Nivash

\\

TA

\\

new lab

\\

sample exercises

\\

o_gate is NOT to be used

)

Leave the top level module type as HDL.

Example: If the project name were “o_gate”, enter “o_gate” as the project name and then click .

For each of the properties given below, click on the ‘

value

’ area and select from the list of

values that appear.

o

Device Family

: Fami

ly of the FPGA/CPLD used. In this laboratory we will be using

the Spartan3E FPGA’s.

o

Device

: The number of the actual device. For this lab you may enter

XC3S250E

(this can be found on the attached prototyping board)

o

Package

: The type of package with the n

umber of pins. The Spartan FPGA used in

this lab is packaged in CP132 package.

o

Speed Grade

: The Speed grade is “

-

4”.

o

Synthesis Tool

:

XST

[VHDL/Verilog]

o

Simulator:

The tool used to simulate and verify the functionality of the design.

Modelsim simulator is

integrated in the Xilinx ISE. Hence choose “Modelsim

-

XE

Verilog” as the simulator or even Xilinx ISE Simulator can be used.

o

Then click on

NEXT

to save the entries.

All project files such as schematics, netlists, Verilog files, VHDL files, etc., will be s

tored in a

subdirectory with the project name.

A project can only have one top level HDL source file (or

schematic). Modules can be added to the project to create a modular,

In order to open an existing project in Xil

inx Tools, select

File

-

>Open

Project

to show the list of

projects on the machine. Choose the project you want and click

OK

.