Vivado please help I am doing my EE class project as the pi

(Vivado)<verilog if-else or case> -> please help

I am doing my EE class project as the picture shows below,

but i dont know how to enter the code for mux and demux(verilog) in Vivado using if-else or case statment (behavioral description of Y)

wrapper mux 13 12 demux 13 Y3 Y3 EN Y2Y2 Y1 YO 12 sdata IO Y1 10 1O S1 Yo S1 So

Solution

//mux

module mux(
I0, I1, I2, I3, S0, S1,Y
);

input I0, I1, I2, I3, S0, S1;
output reg Y;

always @(S1 or S0 or I0 or I1 or I2 or I3)
case ({S1, S0})
2\'b00 : Y=I0;
       2\'b01 : Y=I1;
       2\'b10 : Y=I2;
       2\'b11 : Y=I3;
endcase
endmodule  

//////////////////////////////////////////
//demux

module demux (
En, I0,I1, Y0, Y1, Y2, Y3
);

input En, I0,I1;
output reg Y0, Y1, Y2, Y3;
always @(En,I0, I1)

if (En=1)
   if (I1,I0==00)
   Y0=1,Y1=0,Y2=0,Y3=0;
   else if (I1,I0==01)
   Y0=0,Y1=1,Y2=0,Y3=0;
   else if (I1,I0==10)
   Y0=0,Y1=0,Y2=1,Y3=0;
   else
   Y0=0,Y1=0,Y2=0,Y3=1;
else
Y0=0,Y1=0,Y2=0,Y3=0;  
end

endmodule