| Question 6.6. (TCO 2) In a common anode 7-segment display, the anode should be connected to (Points : 5) | the ground. +5V. +5V in series with a 330 resistor. +5V in series with a 1k resistor. | | Question 7.7. (TCO 1) Which of the following is not a legal VHDL signal type? (Points : 5) | Range Integer Bit Std_Logic | | Question 8.8. (TCO 7) Which one uses a Flip-Flop for its memory cell? (Points : 5) | DRAM EEPROM SRAM All of the above | |
| Question 6.6. (TCO 2) In a common anode 7-segment display, the anode should be connected to (Points : 5) | the ground. +5V. +5V in series with a 330 resistor. +5V in series with a 1k resistor. | | Question 7.7. (TCO 1) Which of the following is not a legal VHDL signal type? (Points : 5) | Range Integer Bit Std_Logic | | Question 8.8. (TCO 7) Which one uses a Flip-Flop for its memory cell? (Points : 5) | DRAM EEPROM SRAM All of the above | |
1) +5V and to drive the system current limiting resistor is needed in series of 330ohms
2) range
type: a built-in or user-defined signal type. Examples of types are bit, bit_vector, Boolean, character, std_logic, and std_ulogic.
3) all the above flipflops contains memory i.e,present and nxt inputs that need static storage access and dynamic access..both read write operations.