NAND gate designing questionSolutionIn PUN for only 1 conduc

NAND gate designing question

Solution

In PUN:

for only 1 conducting pmos transistor (A or B or C or D or E equal to 0 and Y=1, (W/L)p = 8*1 = 8

for all conducting pmos transistor (A=B=C=D=E=1 and Y=0, (W/L)p = 8*5 = 40

In PDN:

for only 1 conducting nmos transistor (A or B or C or D or E equal to 1 and Y=1, (W/L)n = 4/1 = 4

for all conducting nmos transistor (A=B=C=D=E=1 and Y=0, (W/L)n = 4/5 = 0.8