Please solve it with steps and show how you got the answer A

Please solve it with steps and show how you got the answer

A processor uses a 2M Times 8 memory composed of 256K Times 8 memory chips. The memory is controlled by _______ address lines, which are connected to a ______ -bit Memory Address Register (MAR). _____ bits of the address are connected to a _________ decoder. The decoder outputs enable the chips in the memory unit; there are ______ chips; each of which contains _________ memory locations, which are ______ bits wide. A bits of the address are required to select a location within the chip. When a memory location is selected by the address lines, either the contents of that memory location are ______ provided to a ____- -bit Memory Data Register (MDR) in the case of a _______, or the memory location receives the contents of the MDR in the case of a ________.

Solution

Ans are

21

21

3

3

8

8

256K

8

18

8

load

store.

The operations are load and store respectively.