I am not understanding how this VHDL module is a divide by 7

I am not understanding how this VHDL module is a divide by 7 and how the following waveform is completed. Can someone thoroughly explain the code and the waveform? The answer key is provided below:

architecture beh of ProblemOne is signal flops STD LOGIC VECTOR (2 downto 0) signal intsigl STD_LOGIC constant MYCONSTI : STDLOGICVECTOR(2 downto 0 :-X\"6\"; constant MYCONST2 : STDLOGICVECTOR(2 downto 0 := X\"2\"; - - - - begin intsig1

Solution

a) Tclk = n Tpd

Tpd = propogatio delay

Tclk = clocktime