Suppose the DFF from the circuit above was connected directl

Suppose the D-FF from the circuit above was connected directly to a non-ideal inverter, as follows: Assuming that the clock\'s period is 12 ns, as above: What is the maximum inverter gate delay for which this circuit will still function? nanoseconds

Solution

Ans) The inverter gate delay (Ti) should be less than or equal to clock period (Ts)

i.e Ti<=Ts other wise the inverter output is not updated (connected to D) when the second clock comes so as output of D-flip flop which causes unitended operation means circuit not function as expected

So maximum inverter gate delay is T_i=12 ns=Ts