Design a finite state machine FSM that cycles through the la

Design a finite state machine (FSM) that cycles through the last 4 digits of your student ID in a loop. In your design there should be an input that changes the direction of the cycle. Each number of the ID should be displayed on the seven-segment display while the current state of the FSM should be displayed on its corresponding LED. Nonvalid states should keep all LEDs off. For Example, a particular student has the UTEP ID 80-210543. The state diagram and outputs for his design are as follows:

Draft the behavioral Verilog module for the FSM.

Solution

`timescale 1ns/1ns
module student_id_fsm (
                       clock,               //SYSTEM CLOCK
                       student_id,           //STUDENT ID
                       clockwise,           //DIRECTION
                       seven_segment_out,   //SEVENSEGMENT
                       four_bit_led       // LED INDICATION
);

//Port assignments
input clock;
input student_id;
input clockwise;

output seven_segment_out;
output four_bit_led;

//Port types
wire clock;
//integer student_id;
wire clockwise;

reg [6:0] seven_segment_out;
reg [3:0] four_bit_led;

//Temporary variables
integer temp_student_id;
integer state_0,state_1,state_2,state_3;
reg [6:0] seven_segment_state0, seven_segment_state1, seven_segment_state2, seven_segment_state3;
reg [3:0] four_bit_led0, four_bit_led1, four_bit_led2, four_bit_led3;
integer state_value;

always@(student_id) begin                           // LOGIC for the last 4 digits
       temp_student_id = student_id;
          state_3 = temp_student_id % 10;
       temp_student_id = temp_student_id / 10;
          state_2 = temp_student_id % 10;
       temp_student_id = temp_student_id / 10;
          state_1 = temp_student_id % 10;
       temp_student_id = temp_student_id / 10;
          state_0 = temp_student_id % 10;
end

always@(state_0) begin                           //LED pattern and seven segment for last digit
   four_bit_led0 = 4\'b0001;
case (state_0)
0: seven_segment_state0 = \'b1111110;
1: seven_segment_state0 = \'b0000110;
2: seven_segment_state0 = \'b1011011;
3: seven_segment_state0 = \'b1001111;
4: seven_segment_state0 = \'b0100111;
5: seven_segment_state0 = \'b1101101;
6: seven_segment_state0 = \'b1111101;
7: seven_segment_state0 = \'b1000110;
8: seven_segment_state0 = \'b1111111;
9: seven_segment_state0 = \'b1101111;
default: seven_segment_state0 = \'b0000000;
endcase
end

always@(state_1) begin                           //LED pattern and seven segment for digit at 10th place
   four_bit_led1 = 4\'b0010;
case (state_1)
0: seven_segment_state1 = \'b1111110;
1: seven_segment_state1 = \'b0000110;
2: seven_segment_state1 = \'b1011011;
3: seven_segment_state1 = \'b1001111;
4: seven_segment_state1 = \'b0100111;
5: seven_segment_state1 = \'b1101101;
6: seven_segment_state1 = \'b1111101;
7: seven_segment_state1 = \'b1000110;
8: seven_segment_state1 = \'b1111111;
9: seven_segment_state1 = \'b1101111;
default: seven_segment_state1 = \'b0000000;
endcase
end

always@(state_2) begin                         //LED pattern and seven segment for digit at 100th place
   four_bit_led2 = 4\'b0100;
case (state_2)
0: seven_segment_state2 = \'b1111110;
1: seven_segment_state2 = \'b0000110;
2: seven_segment_state2 = \'b1011011;
3: seven_segment_state2 = \'b1001111;
4: seven_segment_state2 = \'b0100111;
5: seven_segment_state2 = \'b1101101;
6: seven_segment_state2 = \'b1111101;
7: seven_segment_state2 = \'b1000110;
8: seven_segment_state2 = \'b1111111;
9: seven_segment_state2 = \'b1101111;
default: seven_segment_state2 = \'b0000000;
endcase
end

always@(state_3) begin                         //LED pattern and seven segment for digit at 1000th place
   four_bit_led3 = 4\'b1000;
case (state_3)
0: seven_segment_state3 = \'b1111110;
1: seven_segment_state3 = \'b0000110;
2: seven_segment_state3 = \'b1011011;
3: seven_segment_state3 = \'b1001111;
4: seven_segment_state3 = \'b0100111;
5: seven_segment_state3 = \'b1101101;
6: seven_segment_state3 = \'b1111101;
7: seven_segment_state3 = \'b1000110;
8: seven_segment_state3 = \'b1111111;
9: seven_segment_state3 = \'b1101111;
default: seven_segment_state3 = \'b0000000;
endcase
end

always@(posedge clock) begin                         //state transitions
   if(clockwise == 1) begin
       if(state_value == 3)
           state_value = 0;
       else
           state_value = state_value + 1;
   end
   else begin
       if(state_value == 0)
           state_value = 3;
       else
           state_value = state_value - 1;
   end
end

always@(state_value) begin                         //LED pattern and seven segment when each state
   case(state_value)
   0 : begin seven_segment_out = seven_segment_state0;
              four_bit_led = four_bit_led0;
       end
   1 : begin seven_segment_out = seven_segment_state1;
              four_bit_led = four_bit_led1;
       end
   2 : begin seven_segment_out = seven_segment_state2;
              four_bit_led = four_bit_led2;
       end
   2 : begin seven_segment_out = seven_segment_state3;
              four_bit_led = four_bit_led3;
       end
    endcase
end  


endmodule