A cache has the following parameters Total Size 512KB Line S

A cache has the following parameters: Total Size (512KB), Line Size (256B), 4-way set associative. How many bits are required for Tag, Index and Offset for a 32-bit Memory address? Assume that the cache is byte-addressable.

Solution

Answer:

set associative:

set associative can has to be divided into 3 tpyes

1) Random: random is a large associative

2)LRU: lru is a smaller associative

3) pseudo associative

for 4- way

=>How many bits are required for Tag, Index and Offset for a 32-bit Memory address?

memory Address space =32 bit

block size=4 words=16bytes

tag =18bits

set index=10bits (tag+ index=28bits)

block offset=4bits

->index means which set

-> tag means which data in block

-> block offset means which word in block

-->both tag and index bits are determine the associative and comes from any whare in block address